1. Field of the Invention
Embodiments of the invention relate to memory devices, and more particularly, in one or more embodiments, to flash memory devices.
2. Description of the Related Art
Flash memory devices are non-volatile memory devices which store information on a semiconductor in a way that needs no power to retain the information stored therein. Among flash memory devices, NAND flash memory devices have been widely used as mass-storage devices because of their high storage densities and low costs.
Referring to FIG. 1A, a conventional NAND flash memory device includes a memory block 100. The memory block 100 includes a plurality of memory cells arranged in a matrix form. The illustrated memory block 100 includes first to m-th bit lines BL0-BLm and first to n-th word lines WL0-WLn. In some arrangements, m can be 32,767 or 65,535, and n can be 32 or 64. The bit lines BL0-BLm extend parallel to one another in a column direction. The word lines WL0-WLn extend parallel to one another in a row direction perpendicular to the column direction. The memory block 100 also includes upper and lower bit line select transistors 120a, 120b for selecting the memory block 100 among a plurality of memory blocks by coupling the selected memory block 100 to bit lines extending outside the memory block 100.
Each bit line includes a string of memory cells 110. For example, the second bit line BL1 includes memory cells 110 connected in series. A bit line and memory cells on the bit line is collectively referred to as a “column” in the context of this document.
The memory cells 110 are floating gate transistors. The floating gate transistors of the memory cells 110 of a column are coupled to one another in series from source to drain. The control gates of the floating gate transistors of memory cells 110 in the same row are coupled to the same word line. Each of the memory cells 110 stores a charge (or a lack of charge), wherein the amount of stored charge can be used to represent, for example, one or more states, and wherein the one or more states can represent one or more digits (for example, bits) of data. The memory cell can be either a single-level cell (SLC) or a multi-level cell (MLC). In one arrangement, the amounts of charge stored in the memory cells 110 may be detected by sensing currents flowing through the floating gate transistors of the memory cells 110. In another arrangement, the amounts of charge stored in the memory cells 110 may be detected by sensing the threshold voltage values of the floating gate transistors of the memory cells 110.
FIG. 1B illustrates a cross-section of the floating gate transistors of the memory cells 110 in the second bit line BL1. The floating gate transistors are formed on a substrate 101. Each of the floating gate transistors includes a source region 111 (which is a drain region for a neighboring transistor), a drain region 112 (which is a source region for a neighboring transistor), a doped channel region 114, a first dielectric 116 (for example, a tunnel oxide) 116, a floating gate 118, a second dielectric 120 (for example, a gate oxide, wherein the tunnel and gate oxide can be formed of the same or different material), and a control gate 122. The first dielectric 116 is formed on the channel region 114 to insulate the floating gate 118 from the channel region 114. The second dielectric 120 physically and electrically separates the floating gate 118 from the control gate 122. The control gate 122 is coupled to an appropriate word line, for example, word line WL1. Electrons can be trapped on the floating gate 118 and be used to store data.
Referring to FIG. 2A, a conventional NAND flash memory device employing an interleaved read scheme will be described. The illustrated NAND flash memory device 200 includes a memory block 210, a top data latch 220, a bottom data latch 230, and a multiplexer 240. The NAND flash memory device 200 also includes a top data line 216 and a bottom data line 217. The NAND flash memory device 200 may include other components, for example, sense amplifiers, address decoders, and a controller for the operation thereof.
The memory block 210 includes a plurality of word lines WL0-WLn, a plurality of bit lines BL0-BLm, and a plurality of memory cells 215. The plurality of word lines WL0-WLn extend substantially parallel to one another. The plurality of bit lines BL0-BLm extend substantially parallel to one another and substantially perpendicular to the word lines WL0-WLn. The memory cells 215 are coupled to corresponding word lines WL0-WLn and bit lines BL0-BLm.
In the illustrated arrangement, the memory block 210 includes a regular section 211 and a repair section 212. The repair section 212 is positioned at the left side of the regular section 211 of the memory block 210, but it will be understood that the repair section 212 can be positioned at any other suitable location of the memory block 210 in other arrangements.
In the regular section 211, odd-numbered columns are electrically coupled to the top data latch 220, and even-numbered columns are electrically coupled to the bottom data latch 220. The columns in the regular section 211 may be referred to as regular columns. The repair section 212 includes a plurality of columns that can replace defective columns in the regular section 211. Similar to the columns in the regular section 211, odd-numbered columns are electrically coupled to the top data latch 220, and even-numbered columns are electrically coupled to the bottom data latch 220. The columns in the repair section 212 may be referred to as redundant columns.
The multiplexer 240 receives outputs from the top data latch 220 via the top data line 216 and the bottom data latch 230 via the bottom data line 217, and selectively provides one of the outputs from the data latches 220, 230 in response to a control signal CS. In one arrangement, the multiplexer 240 alternately provides the outputs from the data latches 220, 230 as data in synchronization with a read clock signal. Such a read scheme can be referred to as an interleaved read scheme.
Referring to FIGS. 2A and 2B, a conventional one-way interleaved read scheme will be described below. During a read operation of the NAND flash memory 200, data digits stored on memory cells on a word line are read from the memory cells by sense amplifiers. To output the data digits, a read clock signal RE# and a bit line address signal ADD are provided to the NAND flash memory 200. In the illustrated example, the read clock signal RE# has a period of T1 and a frequency of f1. The bit line address signal ADD has the same period and frequency as the read clock signal RE#. The bit line address signal ADD provides bit line addresses indicative of the locations of memory cells to be read. In the one-way interleaved read scheme, the read clock signal RE# and the bit line address signal ADD have the same frequency.
During a read operation, a word line is selected first. For example, in FIG. 2A, an i-th word line WLi is selected. Then, bit line addresses are provided to the memory block 210, and data digits stored in memory cells on the selected word line are sensed and transferred to either the top data latch 220 or the bottom data latch 230. Referring to FIG. 2B, for example, during each period of the read clock signal RE#, a bit line address ADD is provided to the top and bottom data latches 220, 230. Upon receiving the bit line address ADD, either of the data latches 220, 230 transfers the stored data digits to the top or bottom data line 216 or 217. For example, when a bit line address signal indicates a second bit line BL1, a data digit stored in the top data latch 220 is coupled to the top data line 216. During a subsequent period of the read clock signal RE#, the data digit stored in the top data line 216 is output through the multiplexer 240.
Meanwhile, during the subsequent period of the read clock signal RE#, a data digit in the bottom data latch 230 is output through the multiplexer 240 during the immediately following period of the read clock signal RE#. In this manner, data digits stored on memory cells on odd-numbered and even-numbered bit lines are alternately output through the multiplexer 240 in a sequential manner.
Referring to FIGS. 2A and 2C, a conventional two-way interleaved read scheme will be described below. During a read operation of the NAND flash memory 200, a read clock signal RE# and an address signal are provided to the NAND flash memory 200. The NAND flash memory 200 generates a bottom bit line address signal BADD and a top bit line address signal TADD, and provides them to the memory block 210 of the NAND flash memory 200. In the illustrated example, the read clock signal RE# has a period of T2 and a frequency of f2. The period T2 of the read clock signal RE# of FIG. 2C may be half of the period T1 of FIG. 2B, and the frequency f2 may be twice higher than the frequency f1 of FIG. 2B. As described above, in the two-way interleaved read scheme, the read clock signal RE# has a frequency about twice higher than that of the bit line address signals TADD, BADD. In a four-way interleaved read scheme, the read clock signal RE# has a frequency about four times higher than that of bit line address signals.
Each of the top and bottom bit line address signals TADD, BADD has a period T1 that is twice longer than the period T2 of the read clock signal RE#. Thus, each of the top and bottom bit line address signals TADD, BADD has a frequency f1 that is half of the frequency f2 of the read clock signal RE#. The top and bottom bit line address signals TADD, BADD have a time difference of T2 or T1/2. The top bit line address signal TADD sequentially provides odd-numbered bit line addresses indicative of the locations of memory cells to be read. Similarly, the bottom bit line address signal BADD sequentially provides even-numbered bit line addresses indicative of the locations of memory cells to be read. In other arrangements, the top bit line address signal TADD and the bottom bit line address signal BADD may provide even-numbered and odd-numbered bit line addresses, respectively.
During a read operation, a word line is selected. For example, in FIG. 2A, an i-th word line WLi is selected. Data digits stored in memory cells on the selected word line WLi are sequentially sensed and transferred to either the top data latch 220 or the bottom data latch 230 according to the bit line address signals TADD, BADD.
In the illustrated arrangement, the top and bottom bit line address signals TADD, BADD are provided to the top and bottom data latches 220, 230, respectively. An odd-numbered bit line address in the top bit line address signal TADD is maintained for two periods of the read clock signal RE#. In other words, the top bit line address signal TADD transitions at every other falling edge of the read clock signal RE# in the illustrated arrangement. During this duration, the top data latch 220 receives and stores a data digit from a selected one of the memory cells on the odd-numbered bit line. For example, when an odd-numbered bit line address indicates a second bit line BL1, a data digit stored on a memory cell coupled to the i-th word line WLi and the second bit line BL1 is read and stored in the top data latch 220. During a subsequent period of the read clock signal RE#, the data digit stored in the top data latch 220 is output through the multiplexer 240.
Meanwhile, an even-numbered bit line address in the bottom bit line address signal BADD is maintained for two periods of the read clock signal RE#. The bottom bit line address signal BADD transitions at different every other falling edge of the read clock signal RE#, as shown in FIG. 2C. Thus, transitions of the bottom bit line address signal BADD and the top bit line address signal TADD alternate with each other. Upon receiving the bottom bit line address signal BADD, the bottom data latch 230 receives and stores a data digit from a selected one of the memory cells on the even-numbered bit line. For example, when a bit line address signal indicates a third bit line BL2, a data digit stored on a data latch coupled to the third bit line BL2 is read, and is transferred to the bottom data line 217. During a subsequent period of the read clock signal RE#, the data digit stored in the bottom data line 217 is output through the multiplexer 240. In this manner, data digits stored on memory cells on odd-numbered and even-numbered bit lines are alternately output through the multiplexer 240. This two-way interleaved read scheme of FIG. 2C provides a faster data read rate than the one-way interleaved read scheme of FIG. 2B. Generally, the more the number of interleave groups, the faster the read operation is.